Active matrix substrates are used widely in active matrix type display devices such as liquid crystal display devices and EL display devices, as well as in a variety of active matrix type sensors and other products. In particular, special attentions are being paid to liquid crystal display devices in which each display pixel is provided with a switching element such as a thin-film transistor (hereinafter abbreviated as TFT) which is a type of field-effect transistors, since these display devices are capable of displaying excellent images without crosstalk between mutually adjacent display pixels even if there is a large number of display pixels.
Such an active matrix type liquid crystal display device primarily includes a liquid crystal display panel and a drive circuit for the panel. The liquid crystal display panel includes a pair of electrode substrates sandwiching a liquid crystal layer. Each electrode substrate has its outer surface covered by a polarizer.
Of the pair of electrode substrates, one is an active matrix substrate called TFT substrate. The TFT substrate includes an insulating substrate made of glass for example, formed with a plurality of data signal lines and a plurality of scanning signal lines crossing with each other in a grid pattern and in addition, a plurality of common electrode lines are formed to extend in parallel to the scanning signal lines. Further, correspondingly to each of the intersections made by the data signal lines and the scanning signal lines, a matrix of pixel circuits are formed. Each pixel circuit includes a pixel electrode for a corresponding pixel that serves to form images to be displayed, pixel capacities formed by the pixel electrode and other elements such as an opposed electrode which will be described later, and a TFT which serves as a switching element. The other electrode substrate, called opposed substrate, is provided by a transparent insulating substrate made of glass for example, having its entire surface laminated with a layer of opposed electrode and then with an alignment film.
The active matrix type liquid crystal display device includes, as a drive circuit for the liquid crystal display panel configured as the above, a scanning signal line drive circuit connected with the scanning signal lines, a data signal line drive circuit connected with the data signal lines, a common electrode line drive circuit connected with the common electrode lines, and an opposed electrode drive circuit connected with the opposed electrode.
The data signal line drive circuit generates, based on image signals received from an outside signal-source for example, a plurality of data signals successively in the form of analog voltage representing pixel values in each horizontal scanning line of the image to be displayed in the liquid crystal display panel, and applies these data signals respectively to the data signal lines in the liquid crystal display panel. The scanning signal line drive circuit selects the scanning signal lines in the liquid crystal display panel sequentially for each horizontal scanning period, and applies an active scanning signal (a voltage for turning ON the TFTs in the pixel circuit) to the selected scanning signal line, in each frame period (each vertical scanning period) for displaying an image on the liquid crystal display panel. The common electrode line drive circuit and the opposed electrode drive circuit apply signals to the common electrode lines and the opposed electrode respectively; these signals give electric potentials that serve as baseline voltages for voltages to be applied to the liquid crystal layer of the liquid crystal display panel.
As described above, the data signal lines are supplied with respective data signals, the scanning signal lines are supplied with respective scanning signals, whereby the pixel electrode in each pixel circuit of the liquid crystal display panel is supplied with a voltage representing the value of the pixel for the image to be displayed, with the potential at the opposed electrode serving as the baseline voltage, and the supplied voltage is held at the pixel capacity in each pixel circuit. Thus, a voltage which equals to the potential difference between each pixel electrode and the opposed electrode is applied to the liquid crystal layer. By controlling optical transmittance based on the applied voltage, the liquid crystal display panel displays an image represented by the image signals received from e.g. an outside signal-source.
FIG. 19 is a circuit diagram which shows a configuration of a pixel circuit in a TFT substrate serving as an active matrix substrate used in a liquid crystal display device as described above. A pixel circuit P(i, j) corresponds to one of the intersections made by the data signal lines and the scanning signal lines, and includes: a TFT 102 which has a source electrode connected with a data signal line S(i) passing the corresponding intersection, and a gate electrode connected with a scanning signal line G(j) passing the same intersection; and a pixel electrode 103 connected with a drain electrode of the TFT 102. The pixel electrode 103 and the opposed electrode form a liquid-crystal capacity Clc. The pixel electrode 103 and a common electrode line CS (j) provided along the scanning signal line G(j) form a common-electrode capacity (may also called “supplemental capacity”) Ccs, and the pixel electrode 103 and the scanning signal line G(j) form a parasitic capacity Cgd.
Hereinafter, reference will be made to FIG. 4-(A) through FIG. 4-(D), FIG. 9 and FIG. 19, to describe a conventional method of driving the above-described TFT substrate in a liquid crystal display device. As a matter of well known fact, liquid crystal displays need AC driving in order to reduce burning images on the screen and display deterioration. The following description of a conventional driving method will assume that a frame-inversion driving method which is a type of AC driving is used.
FIG. 4-(A) through 4-(D) are voltage waveform charts of various voltage signals Vg(j), Vs(i), Vcs, Vcom in the TFT substrate and a waveform of a potential of the pixel electrode (hereinafter may also called “pixel potential”) Vd (i, j) in two consecutive frame periods, i.e. a first frame period TF1 and a second frame period TF2. As shown in FIG. 4-(A), in the first frame period TF1, a voltage serving as a scanning signal (hereinafter called “scanning voltage”) Vgh is applied from the scanning signal line drive circuit to the gate electrode g (i, j) of the TFT 102 in a pixel circuit P(i, j). This turns ON the TFT 102 (into a conductive state), where a voltage serving as a data signal (hereinafter called “data signal voltage”) Vsp applied from the data signal line drive circuit to the data signal line S (i) is supplied to the pixel electrode 103 via the source electrode and the drain electrode of the TFT 102. Thus, the data signal voltage Vsp becomes a positive-polarity voltage with respect to the opposed-electrode potential Vcom (=common electrode potential Vcs), and is written to a pixel capacity Cpix which is formed by the pixel electrode 103 and other electrodes. As shown in FIG. 4-(D), the pixel electrode 103 holds the pixel potential Vdp until a scanning voltage Vgh is applied in the next frame period, i.e. the second frame period TF2. As shown in FIG. 19, the pixel capacity Cpix for holding the pixel potential Vdp is made of the liquid-crystal capacity Clc, the common-electrode capacity Ccs and the parasitic capacity Cgd. Meanwhile, the opposed electrode is set to a predetermined opposed-electrode potential Vcom by the opposed electrode drive circuit. Therefore, the liquid crystal sandwiched between the pixel electrode and the opposed electrode makes a response in accordance with the potential difference between the pixel potential Vdp and the opposed-electrode potential Vcom, achieving a display of the image.
Likewise, as shown in FIG. 4-(A), in the second frame period TF2, upon application of the scanning voltage Vgh from the scanning signal line drive circuit to the gate electrode g(i, j) of the TFT 102 in the pixel circuit P(i, j), the TFT 102 is turned ON, where a data signal voltage Vsn which is applied from the data signal line drive circuit to the data signal line S (i) is supplied to the pixel electrode 103 via the source electrode and the drain electrode of the TFT 102. Thus, the data signal voltage Vsn becomes a negative-polarity voltage with respect to the opposed-electrode potential Vcom (=Vcs), and is written into the pixel capacity Cpix. The pixel electrode 103 holds the pixel potential Vdn until the scanning voltage Vgh is applied in the next frame period. Thus, the liquid crystal sandwiched between the pixel electrode and the opposed electrode makes a response in accordance with the potential difference between the pixel potential Vdn and the opposed-electrode potential Vcom, achieving a display of the image, in an AC driving of a liquid crystal.
As shown in FIG. 19, a parasitic capacity Cgd is unavoidably formed between the scanning signal line G(j) and the pixel electrode 103 in each pixel circuit P(i, j) as a nature of the configuration. Therefore, as shown in FIG. 4-(D), at the time when the active scanning signal voltage, i.e. the scanning voltage Vgh falls down to the non active scanning signal voltage, i.e. the scanning voltage Vgl (represented by a time point ta in the figure), a level shift ΔVd occurs in the pixel potential Vd due to the parasitic capacity Cgd. It should be noted here that in FIG. 4-(D), the level shift of the pixel potential Vd (i, j) in the pixel circuit P(i, j) in the first frame period (in the period when a positive voltage is applied to the liquid crystal layer) TF1 (or more accurately, a level shift at a time point tb which is a time point well after the time point ta) is indicated by a symbol “ΔVdp (i, j)” whereas the level shift of the pixel potential Vd (i, j) in the pixel circuit P(i, j) in the second frame period (the period when a negative voltage is applied to the liquid crystal layer) TF2 is indicated by a symbol “ΔVdn (i, j)”. However, when there is no need to specifically clarify the pixel circuit or the frame period, these level shifts will be indicated by a common symbol “ΔVd” as used in the above (The same will apply hereinafter).
The level shift ΔVd which occurs in the pixel potential Vd due to the parasitic capacity Cgd which is formed unavoidably in the TFT 102 is expressed as follows:ΔVd=Vgpp·Cgd/Cpix Vgpp=Vgl−Vgh Cpix=Clc+Ccs+Cgd The level shift causes such problems as flickers in the displayed image and decreased quality of the displayed image. For this reason, occurrence of the level shift ΔVd as the above is not preferable for liquid crystal display devices which are supposed to achieve ever higher fineness and quality.
Meanwhile, there has been a number of methods (means) proposed for eliminating or reducing the level shift ΔVd as described above. For example, a method has been proposed in which a bias is given to the potential at the opposed electrode so that the level shift ΔVd caused by the parasitic capacity Cgd will be reduced in advance. Also, JP-A Hei 11-281957 Gazette (This corresponds to U.S. Pat. No. 6,359,607, the contents of which is incorporated herein by reference) discloses a method in which the level shift variation in the pixel potential is reduced by controlling the fall of the scanning signal. Further, JP-A 2001-33758 Gazette discloses a method in which the level shift variation in the pixel potential (electric potential of the pixel electrode) by connecting a plurality of variable power sources to the common electrode line.    [Patent Document 1] JP-A 2002-202493 Gazette    [Patent Document 2] JP-A 2001-33758 Gazette    [Patent Document 3] JP-A Hei 11-281957 Gazette    [Patent Document 4] JP-A Hei 11-84428 Gazette    [Patent Document 5] JP-A Hei 10-39328 Gazette    [Patent Document 6] JP-A Hei 5-232512 Gazette